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1 ? fn4806.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 1999, 2003, 2004. all rights reserved all other trademarks mentioned are the property of their respective owners. hc5503prc low cost slic for large telecom switches the hc5503prc is a low cost slic optimized for large telecom switches. it combines a flexible voltage feed architecture with the intersil latch-free di bonded wafer process, to provide a low component count, carrier class solution at very low cost. the re-configurable design permits simple, economical solutions for campus-wide call center and pbx applications. external components can be used in conjunction with the high battery voltage capability to meet the complex impedance and long loop drive requirements of central office switches, worldwide. features ? wide operating battery range (-40v to -58v) ? single additional +5v supply ? 30ma short loop current limit ? ring relay driver ? switch hook and ring trip detect ? low on-hook power consumption ? on-hook transmission ? itu-t longitudinal balance performance ? loop power denial function ? thermal protection ? supports tip, ring or balanced ringing schemes ? low profile so and qfn surface mount packaging ? pb-free available applications ? central office, pbx, call centers ? related literature - an571, using ring sync with hc-5502a and hc-5504 slics ordering information part number temp. range (c) package pkg. dwg. # hc5503prcb 0 to 70 24 ld soic m24.3 hc5503prcbz (note) 0 to 70 24 ld soic (pb-free) m24.3 hc5503prcbz96 (note) 0 to 70 24 ld soic tape & reel (pb-free) m24.3 HC5503PRCR 0 to 70 32 ld 7x7 qfn l32.7x7 HC5503PRCRz (note) 0 to 70 32 ld 7x7 qfn (pb-free) l32.7x7 HC5503PRCRz96 (note) 0 to 70 32 ld 7x7 qfn tape & reel (pb-free) l32.7x7 note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. data sheet june 2004
2 block diagram rd rfs tip tf ring rf v bat v cc bgnd dgnd tx rx shd rs rc pd ring relay driver 4-wire interface vf signal path loop current detector bias logic interface ring trip detector 2-wire interface c1 c 2 agnd thermal limit - + out +in -in hc5503prc
3 absolute maximum rati ngs thermal information maximum continuous supply voltages (v b -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5v (v b +) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7v (v b + - v b -) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75v relay drive voltage (v rd ). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15v operating conditions operating temperature range . . . . . . . . . . . . . . . . . . . 0c to 70c relay driver voltage (v rd ) . . . . . . . . . . . . . . . . . . . . . . . . 5v to 12v positive supply voltage (v b +) . . . . . . . . . . . . . . . . . . 4.75v to 5.25v negative supply voltage (v b -) . . . . . . . . . . . . . . . . . . . -40v to -58v high level logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4v low level logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6v subscriber loop resistance . . . . . . . . . . . . . . . . . . . 200 ? - 1800 ? thermal resistance (typical, note 2, 3) ja (c/w) 24 lead soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 32 lead 7x7 qfn . . . . . . . . . . . . . . . . . . . . . . . . . . 32 maximum junction temperature plastic . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) die characteristics transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 diode count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 die dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102 substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . connected process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bipolar-di caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. absolute maximum ratings are limiting values, applied individual ly, beyond which the serviceability of the circuit may be imp aired. functional operability under any of these conditi ons is not necessarily implied. 2. ja is measured with the component mount ed on an evaluation pc board in free air. 3. ja for the qfn package is measured in free air with the com ponent mounted on a high effective thermal conductivity test board wit h direct attach features including conductive thermal vias. see tech brief tb379 and tb389 for additional information and board layout c onsideration electrical specifications unless otherwise specified, v b - = -48v, v b + = 5v, ag = bg = dg = 0v, r p = 50 ? , r s = 100 ? , typical parameters. t a = 25c. min-max parameters are over operating temperature range parameter conditions min typ max units on hook power dissipation i long = 0 (note 4) - 113 - mw off hook power dissipation r l = 600 ? , i long = 0 (notes 3, 4) - 750 - mw on hook i b +r l = , i long = 0 - 1.4 - ma off hook i b +r l = 600 ? , i long = 0 - 2.8 - ma on hook i b -r l = , i long = 0 - 2.2 - ma off hook i b -r l = 600 ? , i long = 0 - 31 - ma off hook loop current r l = 1800 ? (i loop = 0) 18 - - ma off hook loop current r l = 200 ? , i long = 0 (note 3) 25 30 35 ma fault currents tip to ground -27-ma ring to ground -55-ma tip to ring -30-ma tip and ring to ground -69-ma ring relay drive v ol i ol = 62ma - 0.2 0.5 v ring relay driver off leakage v rd = 12v, rc = 1 = high, t a = 25c - - 100 a dc ring trip threshold 8.1 10.8 13.5 ma switch hook detection threshold 5.0 7.5 10 ma loop current during power denial r l = 200 ? -3.2-ma dial pulse distortion (note 4) 0 - 0.5 ms receive input impedance (note 4) - 110 - k ? transmit output impedance (note 4) - 10 20 ? hc5503prc
4 2-wire return loss (referenced to 600 ? + 2.16 f), r p = r s = 150 ? (note 4) sr l lo - 15.5 - db er l -24-db sr l hi -31-db longitudinal balance 1v rms 200hz - 3400hz, (note 4) ieee method 0c t a 75c, r p = r s = 150 ? 2-wire off hook (note 4) 53 58 - db 2-wire on hook (note 4) 53 58 - db 4-wire off hook 50 58 - db insertion loss at 1khz, 0dbm input level, referenced 600 ?, r p =r s = 150 ? 2-wire to 4-wire, 4-wire to 2-wire - 0.05 0.2 db frequency response 200 - 3400hz referenced to absolute loss at 1khz and 0dbm signal level, r p = r s = 150 ? (note 4) - 0.02 0.05 db idle channel noise r p = r s = 150 ? (note 4) 2-wire to 4-wire, 4-wire to 2-wire -15dbrnc --89-85dbm0p absolute delay r p = r s = 150 ? (note 4) 2-wire to 4-wire, 4-wire to 2-wire --2 s trans hybrid loss balance network set up for 600 ? termination at 1khz, r p = r s = 150 ? (note 4) 30 40 - db overload level v b + = +5v, r p = r s = 150 ? (note 4) 2-wire to 4-wire, 4- wire to 2-wire 1.5 - - v peak level linearity 2-wire to 4-wire, 4-wire to 2-wire (note 4) at 1khz, (note 4) referenced to 0dbm level, r p = r s = 150 ? +3 to -40dbm - - 0.05 db -40 to -50dbm - - 0.1 db -50 to -55dbm - - 0.3 db power supply rejection ratio r p = r s = 150 ? (note 4) 30 - 60hz, r l = 600 ? v b + to 2-wire 15 - - db v b + to transmit 15 - - db v b - to 2-wire 15 - - db v b - to transmit 15 - - db v b + to 2-wire 200 - 16khz, r l = 600 ?, r p = r s = 150 ? 30 - - db v b + to transmit 30 - - db v b - to 2-wire 30 - - db v b - to transmit 30 - - db logic input current (rs, rc , pd )0v v in 5v - - 100 a logic inputs logic ?0? v il --0.8v logic ?1? v ih 2.0 - 5.5 v logic outputs logic ?0? v ol i load 800 a, v b + = 5v - 0.1 0.5 v logic ?1? v oh i load 40 a, v b + = 5v 2.7 - 5.0 v electrical specifications unless otherwise specified, v b - = -48v, v b + = 5v, ag = bg = dg = 0v, r p = 50 ? , r s = 100 ? , typical parameters. t a = 25c. min-max parameters are over operating temperature range (continued) parameter conditions min typ max units hc5503prc
5 uncommitted op amp specifications input offset voltage - 5-mv input offset current - 10 - na input bias current -20-na differential input resistance (note 4) - 1 - m ? output voltage swing r l = 10k, v b + = 5v - 3-v peak output resistance a vcl = 1 (note 4) - 10 - ? small signal gbw (note 4) - 1 - mhz notes: 4. i long = longitudinal current. 5. these parameters are controlled by design or process parameter s and are not directly tested. these parameters are characteriz ed upon initial design release, upon design changes which woul d affect these characteristics, and at intervals to assure product quality and sp ecification compliance. electrical specifications unless otherwise specified, v b - = -48v, v b + = 5v, ag = bg = dg = 0v, r p = 50 ? , r s = 100 ? , typical parameters. t a = 25c. min-max parameters are over operating temperature range (continued) parameter conditions min typ max units pin descriptions 24 pin dip/soic 7 x 7 qfn symbol description 1 28 tip an analog input connected to the tip (more positive) side of the subscriber l oop through a sense resistor (r s ) and a ring relay contact. functions with the ring te rminal to receive voice signals from the telephone and for loop monitoring purposes. 2 31 ring an analog input connected to the ring (more negat ive) side of the subscriber loop through a sense resistor (r s ) and a ring relay contact. functions with the ti p terminal to receive voice signals from the telephone and for loop monitoring purposes. 3 32 rfs senses ring side of loop for ground key and ring trip detection. during ringing, the ring signal is inserted into the line at this node and rf is isolated from rfs via a relay. 41v b + positive voltage source - most positive supply. v b + is typically. 53c 1 capacitor #1 - an external capacitor to be connec ted between this terminal and analog ground. required for proper operation of the loop current limiting function, and for filtering v b -. typical value is 0.3 f, 30v. 6 4 dg digital ground - to be connected to zero potential a nd serves as a reference for all digital inputs and outputs on the slic microcircuit. 7 5 rs ring synchronization input - a ttl - compatible clock input. the clock shoul d be arranged such that a positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the rfs terminal. for tip side injected systems, the rs pu lse should occur on the negat ive going zero crossing and for ring injected systems, on the positive going zero crossing. this ensures that the ring relay activates and deactivates when the instantaneous ring vo ltage is near zero. if synchronization is not required, the pin should be tied to 5v. 86rd relay driver - a low active open collector logic out put. when enabled, the external ring relay is energized. 9 7, 8 tf tip feed - a low impedance analog output connected to the tip terminal through a sense resistor (r s ). functions with the rf terminal to provide loop cu rrent, feed voice signals to the telephone set, and sink longitudinal current. 10 9, 10 rf ring feed - a low impedance analog output connec ted to the ring terminal through a sense resistor (r s ). functions with the tf terminal to provide l oop current, feed voice signals to the telephone set, and sink longitudinal current. 11 11 v b - negative voltage source - most negative supply. v b - is typically -48v with an operational range of -42v to -58v. frequently referred to as ?battery?. 12 12 bg battery ground - to be connected to zero potential. all loop current and some quiescent current flows into this ground terminal. 13 13 shd switch hook detection - a low active ls ttl - com patible logic output. this output is enabled for loop currents exceeding the switch hook threshold. 14 14,19 nc used during product ion test. leave disconnected. hc5503prc
6 15 15 pd power denial - a low active ttl - compatible l ogic input. when enabled, the ring feed voltage collapses to the tip feed voltage (~4v). the dc feed is disabled, but the ac transmission is maintained. the switch hook detect (shd ) is not necessarily valid, and the relay driver (rd ) output is disabled. 16 16 rc ring command - a low active ttl - compatible logic input. when enabled, the relay driver (rd ) output goes low on the next high level of the ring sync (rs) input, as long as the slic is not in the power denial state (pd = 0) or the subscriber is not already off- hook (shd = 0). 17 nc leave disconnected. 18 20 out the analog output of the spare operational amplifier. 19 21 -in the inverting analog input of the spare operational amplifier. 20 22 +in the non-inverting analog input of the spare operational amplifier. 21 23 rx receive input, four wire side - a high impedance analog input which is inter nally biased. capacitive coupling to this input is required. ac signals appeari ng at this input differentially drive the tip feed and ring feed terminals. 22 25 c 2 capacitor #2 - an external capacitor to be c onnected between this terminal and analog ground. this capacitor is required for the proper operation of ring trip detection. recommended value 0.82 f 10% 10v non-polarized. 23 26 ag analog ground - to be connected to zero potential and serves as a reference for the transmit output (tx) and receive input (rx) terminals. 24 27 tx transmit output, four wire side - a low im pedance analog output proportional to the loop current. transhybrid balancing must be performed beyond this out put to completely implement two to four wire conversion. this output is unbalanced and referenced to analog ground. since the dc level of this output varies with loop current, capacitive c oupling to the next stage is essential. 2, 17, 18,24, 29, 30, nc no internal connection. note: all grounds (ag, bg, and dg) must be applied before v b + or v b -. failure to do so may result in premature failure of the part. if a user wishes to run separate grounds off a line card, the ag must be applied first. pin descriptions (continued) 24 pin dip/soic 7 x 7 qfn symbol description hc5503prc
7 functional diagram + diff amp + op amp loop monitoring ring control 2-wire loop secondary protection line drivers tip ring v b - v b - pd power denial r p ring r s rf bg tf tip rd rc rs ring sync ring command ring trip shd tx transmit output out +in -in rx receive input slic microcircuit 1/2 ring relay v b - ring voltage rfs 1/2 ring relay r s switch hook detection -1 +1 battery feed loop current limiter r p r s : 100 ? ; 1/2w to 2w depending on surge requirements r p :50 ? ; 1/2w to 2w depending on surge requirements hc5503prc
8 slic functional schematic soic pin numbers shown v b2 v b1 v b2 v b3 v b4 v b5 5v i b1 i b2 i b3 i b4 i b5 i b6 i b7 i b8 v bat i b9 i b10 i b11 v b + v b + a-100 transv?l i/v amp - + i b6 r 6 r 5 r 11 v b + r 7 r 8 r 10 r 9 r 22 r 23 r 3 r 4 r 1 r 2 r 16 r 15 v bat v bat r 12 v bat v b + a-200 long?l i/v amp i b7 - + r 20 v bat v b + a-400 tip feed amp i b4 - + ring feed sense v bat v bat 5v v b4 i b8 ring trip detector + switch hook v b1 i b6 + r 18 detector v b + q d28 q d27 v bat - + - gnd shorts current limiting i b1 v b3 thermal limiting v b5 sttl and logic interface rfc sh gk v b5 - + i b2 load current limiting r 14 r 13 v bat v bat/2 reference r 21 v bat a-300 ring feed amp i b5 - + ring rf tip tf 10 2 3 1 9 rx c2 v bat bat ana dig v b + gnd gnd gnd 21 22 11 12 23 6 4 + - out 20 19 18 a-500 op amp v bat i b3 v b + v b + 5v i b10 v bat pd 15 rc shd nc nc 16 13 17 14 tx c1 rs rd 8 7 24 5 r 17 v b2 v b + r 19 v bat q d3 q d36 voltage and current bias network hc5503prc
9 surge protection the slic device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. the voltage withstand capability of pins ?tip?, ?ring? and ?rfs? is 450v with respect to ground, as shown in table 1. this device is intended for use with an appropriate secondary protection circuit scheme. the slic will withstand longitudinal currents up to a maximum or 30ma rms , 15ma rms per leg, without any performance degradation. logic gate schematic 15 5 6 12 4 16 13 a b c c b a ttl to sttl ttl to sttl ttl to sttl to r 21 shd rd pd rc rs ttl to sttl delay logic bias relay driver sh gk 11 14 3 9 7 8 10 2 1 schottky logic table 1. parameter test condition performance (max) units longitudinal surge 10 s rise/ 1000 s fall 450 (plastic) v peak metallic surge 10 s rise/ 1000 s fall 450 (plastic) v peak t/gnd r/gnd 10 s rise/ 1000 s fall 450 (plastic) v peak 50/60hz current t/gnd r/gnd 11 cycles limited to 10a rms 315 (plastic) v rms hc5503prc
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com hc5503prc small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 o 8 o 0 o 8 o - rev. 0 12/93
11 hc5503prc quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l32.7x7 32 lead quad flat no-lead plastic package (compliant to jedec mo-220vkkc issue c) symbol millimeters notes min typ max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 7.00 bsc - d1 6.75 bsc 9 d2 4.55 4.70 4.85 7, 8 e 7.00 bsc - e1 6.75 bsc 9 e2 4.55 4.70 4.85 7, 8 e 0.65 bsc - k0.25--- l 0.50 0.60 0.75 8 l1 - - 0.15 10 n322 nd 8 3 ne 8 3 p- -0.609 --129 rev. 4 8/03 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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